The present invention generally relates to master slice type integrated circuits, and in particular to improvements in input/output cells formed in a peripheral region on a semiconductor chip of a master slice type integrated circuit.
A master slice type integrated circuit has been widely researched and manufactured. A complementary metal oxide semiconductor (CMOS) gate array is an example of applications of the master slice type integrated circuit. The master slice type integrated circuit comprises a semiconductor chip on which there are formed basic cells arrayed like a matrix and input/output cells arranged in a peripheral region on the chip outside a region in which the basic cell matrix is formed. Each basic cell is generally constituted by a plurality of transistors. Pre-processing for forming transistors is commonly carried out. At an interconnecting step which is a last step of steps for producing the master slice type integrated circuit, arbitrary routing of interconnection lines may be selected. Therefore, desired logic circuits can be constituted by interconnecting the basic cells and I/O cells in accordance with user's requests.
The input/output cells (hereafter simply referred to as I/O cells) are used to provide the logic circuits on the chip with signals which are provided by an external circuit and feed output signals of the logic circuits to the external circuit. Each of the I/O cells comprises an input wiring region through which an input interconnecting line extending towards the basic cell matrix is passed, an input protecting circuit region for forming an input protecting circuit for protecting an input buffer provided in the basic cell matrix against electrostatic discharge, an output circuit region for constituting an output buffer, and a bonding pad for connecting the input or output buffers to a terminal for the connection to the external circuit. Both the input wiring region and the input protecting circuit region form an input circuit region. As described before, these elements for constituting the I/O cell are arranged in the peripheral region on the chip. An interconnection to build circuits of the I/O cell may be also arbitrarily made in accordance with a user's specification. Generally, the interconnection between the I/O cell circuits is made by use of a first (lower) layer metallization deposited on an insulator on a silicon crystal of the chip. In the peripheral region of the chip, there is also provided a power supply line for providing the logic circuits constituted by the combination of the basic cells with the power. The power supply line is formed by a second (upper) metallization which is deposited on an insulator coated on the first metallization.
However, the conventional master slice type integrated circuit has the following disadvantages. All of the I/O cells have the same configuration to facilitate the automatic routing design of the interconnections. That is, the input wiring region, the output circuit region, and the input protecting circuit region of all I/O cell are respectively the same as those of other I/O cells from the view point of size, position and so on. The fact that all the I/O cells have the same configuration degrades the efficiency in utilizing the I/O cells, i.e., reduces the number of utilizable I/O cells. This means that the degree of flexibility of the design is not sufficient to satisfy the user's requests.